REALIZATION OF DYNAMIC DOUBLE-TILE COMPARATOR PROPOSED FOR HIGH SPEED 4G NETWORK COMS APPLICATION
Keywords:
dynamic clocked comparator, Double-tail comparator, low-power analog design high-speed analog-to-digital converters (ADCs).Abstract
In the current circumstance, necessity for ultra-low-control, domain capable and quick easy to-cutting edge converters (ADCs) is pushing toward the use of component Clocked regenerative comparators to improve the power profitability and pace. In this work, we changed the structure of the Dynamic Double-Tile Comparator by adding couple of additional transistors to the present structure. The proposed changed Double-Tail Dynamic Comparator is used for fast operations even as a piece of little supplies voltages. We can execute the proposed structure and existing structures of Dynamic Comparator in Mentor Graphics Tool. From entertainment results in 0.18-μm CMOS advancement, we find that the proposed arrangement yields less Delay than the present structures.
