DESIGN OF VOLTAGE-MODE INSTRUMENTATION AMPLIFIERS FOR ECG SIGNALS USING CMOS TECHNOLOGY

Abstract

Design and implementation of four monolithic voltage-mode instrumentation amplifier (in-amp) topologies are studied and discussed in this paper. These in-amp topologies utilize op-amps with rail-to-rail input and output stages. As recommended in [1], the operational amplifier (op-amp) implementation used in this study employs a complementary differential pair with n-type metal-oxide semiconductor (NMOS) cascode load input stage and a push-pull inverter output stage. The op-amp is designed to achieve the highest possible common-mode rejection ratio (CMRR) while maintaining stability. A compensation network is also designed to maintain stability when the designed op-amp is incorporated into the in-amp. The four voltage-mode in-amp topologies are designed for handling biomedical signals specifically that of the Electrocardiogram (ECG), and are implemented in a 0.25μm Complementary Metal-Oxide Semiconductor (CMOS) process. Simulations achieved a CMRR of about 90 dB for all topologies, with the 2-op-amp in-amp showing an advantage over its 3-op-amp counterparts in terms of power consumption. The simulations are obtained for a gain of 200 and power supply of 2.5V.